
sizeof:     file format elf64-littleaarch64


Disassembly of section .init:

0000000000400480 <_init>:
  400480:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  400484:	910003fd 	mov	x29, sp
  400488:	94000030 	bl	400548 <call_weak_fn>
  40048c:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400490:	d65f03c0 	ret

Disassembly of section .plt:

00000000004004a0 <.plt>:
  4004a0:	a9bf7bf0 	stp	x16, x30, [sp, #-16]!
  4004a4:	90000090 	adrp	x16, 410000 <__FRAME_END__+0xf538>
  4004a8:	f947fe11 	ldr	x17, [x16, #4088]
  4004ac:	913fe210 	add	x16, x16, #0xff8
  4004b0:	d61f0220 	br	x17
  4004b4:	d503201f 	nop
  4004b8:	d503201f 	nop
  4004bc:	d503201f 	nop

00000000004004c0 <__libc_start_main@plt>:
  4004c0:	b0000090 	adrp	x16, 411000 <__libc_start_main@GLIBC_2.17>
  4004c4:	f9400211 	ldr	x17, [x16]
  4004c8:	91000210 	add	x16, x16, #0x0
  4004cc:	d61f0220 	br	x17

00000000004004d0 <__gmon_start__@plt>:
  4004d0:	b0000090 	adrp	x16, 411000 <__libc_start_main@GLIBC_2.17>
  4004d4:	f9400611 	ldr	x17, [x16, #8]
  4004d8:	91002210 	add	x16, x16, #0x8
  4004dc:	d61f0220 	br	x17

00000000004004e0 <abort@plt>:
  4004e0:	b0000090 	adrp	x16, 411000 <__libc_start_main@GLIBC_2.17>
  4004e4:	f9400a11 	ldr	x17, [x16, #16]
  4004e8:	91004210 	add	x16, x16, #0x10
  4004ec:	d61f0220 	br	x17

00000000004004f0 <printf@plt>:
  4004f0:	b0000090 	adrp	x16, 411000 <__libc_start_main@GLIBC_2.17>
  4004f4:	f9400e11 	ldr	x17, [x16, #24]
  4004f8:	91006210 	add	x16, x16, #0x18
  4004fc:	d61f0220 	br	x17

Disassembly of section .text:

0000000000400500 <_start>:
  400500:	d280001d 	mov	x29, #0x0                   	// #0
  400504:	d280001e 	mov	x30, #0x0                   	// #0
  400508:	aa0003e5 	mov	x5, x0
  40050c:	f94003e1 	ldr	x1, [sp]
  400510:	910023e2 	add	x2, sp, #0x8
  400514:	910003e6 	mov	x6, sp
  400518:	580000c0 	ldr	x0, 400530 <_start+0x30>
  40051c:	580000e3 	ldr	x3, 400538 <_start+0x38>
  400520:	58000104 	ldr	x4, 400540 <_start+0x40>
  400524:	97ffffe7 	bl	4004c0 <__libc_start_main@plt>
  400528:	97ffffee 	bl	4004e0 <abort@plt>
  40052c:	00000000 	.inst	0x00000000 ; undefined
  400530:	00400870 	.word	0x00400870
  400534:	00000000 	.word	0x00000000
  400538:	00400898 	.word	0x00400898
  40053c:	00000000 	.word	0x00000000
  400540:	00400918 	.word	0x00400918
  400544:	00000000 	.word	0x00000000

0000000000400548 <call_weak_fn>:
  400548:	90000080 	adrp	x0, 410000 <__FRAME_END__+0xf538>
  40054c:	f947f000 	ldr	x0, [x0, #4064]
  400550:	b4000040 	cbz	x0, 400558 <call_weak_fn+0x10>
  400554:	17ffffdf 	b	4004d0 <__gmon_start__@plt>
  400558:	d65f03c0 	ret
  40055c:	00000000 	.inst	0x00000000 ; undefined

0000000000400560 <deregister_tm_clones>:
  400560:	b0000080 	adrp	x0, 411000 <__libc_start_main@GLIBC_2.17>
  400564:	91010000 	add	x0, x0, #0x40
  400568:	b0000081 	adrp	x1, 411000 <__libc_start_main@GLIBC_2.17>
  40056c:	91010021 	add	x1, x1, #0x40
  400570:	eb00003f 	cmp	x1, x0
  400574:	540000a0 	b.eq	400588 <deregister_tm_clones+0x28>  // b.none
  400578:	90000001 	adrp	x1, 400000 <_init-0x480>
  40057c:	f9449c21 	ldr	x1, [x1, #2360]
  400580:	b4000041 	cbz	x1, 400588 <deregister_tm_clones+0x28>
  400584:	d61f0020 	br	x1
  400588:	d65f03c0 	ret
  40058c:	d503201f 	nop

0000000000400590 <register_tm_clones>:
  400590:	b0000080 	adrp	x0, 411000 <__libc_start_main@GLIBC_2.17>
  400594:	91010000 	add	x0, x0, #0x40
  400598:	b0000081 	adrp	x1, 411000 <__libc_start_main@GLIBC_2.17>
  40059c:	91010021 	add	x1, x1, #0x40
  4005a0:	cb000021 	sub	x1, x1, x0
  4005a4:	9343fc21 	asr	x1, x1, #3
  4005a8:	8b41fc21 	add	x1, x1, x1, lsr #63
  4005ac:	9341fc21 	asr	x1, x1, #1
  4005b0:	b40000a1 	cbz	x1, 4005c4 <register_tm_clones+0x34>
  4005b4:	90000002 	adrp	x2, 400000 <_init-0x480>
  4005b8:	f944a042 	ldr	x2, [x2, #2368]
  4005bc:	b4000042 	cbz	x2, 4005c4 <register_tm_clones+0x34>
  4005c0:	d61f0040 	br	x2
  4005c4:	d65f03c0 	ret

00000000004005c8 <__do_global_dtors_aux>:
  4005c8:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  4005cc:	910003fd 	mov	x29, sp
  4005d0:	f9000bf3 	str	x19, [sp, #16]
  4005d4:	b0000093 	adrp	x19, 411000 <__libc_start_main@GLIBC_2.17>
  4005d8:	39410260 	ldrb	w0, [x19, #64]
  4005dc:	35000080 	cbnz	w0, 4005ec <__do_global_dtors_aux+0x24>
  4005e0:	97ffffe0 	bl	400560 <deregister_tm_clones>
  4005e4:	52800020 	mov	w0, #0x1                   	// #1
  4005e8:	39010260 	strb	w0, [x19, #64]
  4005ec:	f9400bf3 	ldr	x19, [sp, #16]
  4005f0:	a8c27bfd 	ldp	x29, x30, [sp], #32
  4005f4:	d65f03c0 	ret

00000000004005f8 <frame_dummy>:
  4005f8:	17ffffe6 	b	400590 <register_tm_clones>

00000000004005fc <size_len>:
  4005fc:	a9a57bfd 	stp	x29, x30, [sp, #-432]!
  400600:	910003fd 	mov	x29, sp
  400604:	f900d7bf 	str	xzr, [x29, #424]
  400608:	90000000 	adrp	x0, 400000 <_init-0x480>
  40060c:	91252000 	add	x0, x0, #0x948
  400610:	f900d3a0 	str	x0, [x29, #416]
  400614:	90000000 	adrp	x0, 400000 <_init-0x480>
  400618:	91254000 	add	x0, x0, #0x950
  40061c:	d2800101 	mov	x1, #0x8                   	// #8
  400620:	97ffffb4 	bl	4004f0 <printf@plt>
  400624:	90000000 	adrp	x0, 400000 <_init-0x480>
  400628:	9125a000 	add	x0, x0, #0x968
  40062c:	d2800081 	mov	x1, #0x4                   	// #4
  400630:	97ffffb0 	bl	4004f0 <printf@plt>
  400634:	90000000 	adrp	x0, 400000 <_init-0x480>
  400638:	91260000 	add	x0, x0, #0x980
  40063c:	d2803201 	mov	x1, #0x190                 	// #400
  400640:	97ffffac 	bl	4004f0 <printf@plt>
  400644:	90000000 	adrp	x0, 400000 <_init-0x480>
  400648:	91264000 	add	x0, x0, #0x990
  40064c:	d2800081 	mov	x1, #0x4                   	// #4
  400650:	97ffffa8 	bl	4004f0 <printf@plt>
  400654:	90000000 	adrp	x0, 400000 <_init-0x480>
  400658:	9126a000 	add	x0, x0, #0x9a8
  40065c:	d2800101 	mov	x1, #0x8                   	// #8
  400660:	97ffffa4 	bl	4004f0 <printf@plt>
  400664:	90000000 	adrp	x0, 400000 <_init-0x480>
  400668:	91270000 	add	x0, x0, #0x9c0
  40066c:	d2800101 	mov	x1, #0x8                   	// #8
  400670:	97ffffa0 	bl	4004f0 <printf@plt>
  400674:	90000000 	adrp	x0, 400000 <_init-0x480>
  400678:	91276000 	add	x0, x0, #0x9d8
  40067c:	d2800101 	mov	x1, #0x8                   	// #8
  400680:	97ffff9c 	bl	4004f0 <printf@plt>
  400684:	90000000 	adrp	x0, 400000 <_init-0x480>
  400688:	9127c000 	add	x0, x0, #0x9f0
  40068c:	d2800101 	mov	x1, #0x8                   	// #8
  400690:	97ffff98 	bl	4004f0 <printf@plt>
  400694:	90000000 	adrp	x0, 400000 <_init-0x480>
  400698:	91280000 	add	x0, x0, #0xa00
  40069c:	d2800021 	mov	x1, #0x1                   	// #1
  4006a0:	97ffff94 	bl	4004f0 <printf@plt>
  4006a4:	d503201f 	nop
  4006a8:	a8db7bfd 	ldp	x29, x30, [sp], #432
  4006ac:	d65f03c0 	ret

00000000004006b0 <fun>:
  4006b0:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  4006b4:	910003fd 	mov	x29, sp
  4006b8:	f9000fa0 	str	x0, [x29, #24]
  4006bc:	90000000 	adrp	x0, 400000 <_init-0x480>
  4006c0:	91286000 	add	x0, x0, #0xa18
  4006c4:	d2800101 	mov	x1, #0x8                   	// #8
  4006c8:	97ffff8a 	bl	4004f0 <printf@plt>
  4006cc:	d503201f 	nop
  4006d0:	a8c27bfd 	ldp	x29, x30, [sp], #32
  4006d4:	d65f03c0 	ret

00000000004006d8 <array_cal>:
  4006d8:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  4006dc:	910003fd 	mov	x29, sp
  4006e0:	90000000 	adrp	x0, 400000 <_init-0x480>
  4006e4:	91296000 	add	x0, x0, #0xa58
  4006e8:	910063a2 	add	x2, x29, #0x18
  4006ec:	aa0003e3 	mov	x3, x0
  4006f0:	a9400460 	ldp	x0, x1, [x3]
  4006f4:	a9000440 	stp	x0, x1, [x2]
  4006f8:	b9401060 	ldr	w0, [x3, #16]
  4006fc:	b9001040 	str	w0, [x2, #16]
  400700:	910063a0 	add	x0, x29, #0x18
  400704:	91005000 	add	x0, x0, #0x14
  400708:	f9001fa0 	str	x0, [x29, #56]
  40070c:	910063a0 	add	x0, x29, #0x18
  400710:	11000400 	add	w0, w0, #0x1
  400714:	93407c00 	sxtw	x0, w0
  400718:	f9001ba0 	str	x0, [x29, #48]
  40071c:	910063a0 	add	x0, x29, #0x18
  400720:	91005000 	add	x0, x0, #0x14
  400724:	b9002fa0 	str	w0, [x29, #44]
  400728:	f9401fa0 	ldr	x0, [x29, #56]
  40072c:	b9400001 	ldr	w1, [x0]
  400730:	f9401fa0 	ldr	x0, [x29, #56]
  400734:	d1001000 	sub	x0, x0, #0x4
  400738:	b9400002 	ldr	w2, [x0]
  40073c:	f9401ba0 	ldr	x0, [x29, #48]
  400740:	b9400003 	ldr	w3, [x0]
  400744:	90000000 	adrp	x0, 400000 <_init-0x480>
  400748:	9128e000 	add	x0, x0, #0xa38
  40074c:	2a0303e4 	mov	w4, w3
  400750:	2a0203e3 	mov	w3, w2
  400754:	2a0103e2 	mov	w2, w1
  400758:	b9402fa1 	ldr	w1, [x29, #44]
  40075c:	97ffff65 	bl	4004f0 <printf@plt>
  400760:	52800000 	mov	w0, #0x0                   	// #0
  400764:	a8c47bfd 	ldp	x29, x30, [sp], #64
  400768:	d65f03c0 	ret

000000000040076c <enum_color_sizeof>:
  40076c:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  400770:	910003fd 	mov	x29, sp
  400774:	90000000 	adrp	x0, 400000 <_init-0x480>
  400778:	9129c000 	add	x0, x0, #0xa70
  40077c:	d2800081 	mov	x1, #0x4                   	// #4
  400780:	97ffff5c 	bl	4004f0 <printf@plt>
  400784:	d503201f 	nop
  400788:	a8c17bfd 	ldp	x29, x30, [sp], #16
  40078c:	d65f03c0 	ret

0000000000400790 <a_and_a>:
  400790:	d10083ff 	sub	sp, sp, #0x20
  400794:	b9000bff 	str	wzr, [sp, #8]
  400798:	390033ff 	strb	wzr, [sp, #12]
  40079c:	52800c20 	mov	w0, #0x61                  	// #97
  4007a0:	390023e0 	strb	w0, [sp, #8]
  4007a4:	52800c40 	mov	w0, #0x62                  	// #98
  4007a8:	390027e0 	strb	w0, [sp, #9]
  4007ac:	52800c60 	mov	w0, #0x63                  	// #99
  4007b0:	39002be0 	strb	w0, [sp, #10]
  4007b4:	52800c80 	mov	w0, #0x64                  	// #100
  4007b8:	39002fe0 	strb	w0, [sp, #11]
  4007bc:	910023e0 	add	x0, sp, #0x8
  4007c0:	f9000fe0 	str	x0, [sp, #24]
  4007c4:	910023e0 	add	x0, sp, #0x8
  4007c8:	f9000be0 	str	x0, [sp, #16]
  4007cc:	d503201f 	nop
  4007d0:	910083ff 	add	sp, sp, #0x20
  4007d4:	d65f03c0 	ret

00000000004007d8 <planar_array>:
  4007d8:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  4007dc:	910003fd 	mov	x29, sp
  4007e0:	a9017fbf 	stp	xzr, xzr, [x29, #16]
  4007e4:	f90013bf 	str	xzr, [x29, #32]
  4007e8:	52800020 	mov	w0, #0x1                   	// #1
  4007ec:	b90013a0 	str	w0, [x29, #16]
  4007f0:	52800060 	mov	w0, #0x3                   	// #3
  4007f4:	b90017a0 	str	w0, [x29, #20]
  4007f8:	528000a0 	mov	w0, #0x5                   	// #5
  4007fc:	b9001ba0 	str	w0, [x29, #24]
  400800:	910043a0 	add	x0, x29, #0x10
  400804:	f90017a0 	str	x0, [x29, #40]
  400808:	f94017a0 	ldr	x0, [x29, #40]
  40080c:	b9400002 	ldr	w2, [x0]
  400810:	90000000 	adrp	x0, 400000 <_init-0x480>
  400814:	912ae001 	add	x1, x0, #0xab8
  400818:	90000000 	adrp	x0, 400000 <_init-0x480>
  40081c:	912a2000 	add	x0, x0, #0xa88
  400820:	97ffff34 	bl	4004f0 <printf@plt>
  400824:	90000000 	adrp	x0, 400000 <_init-0x480>
  400828:	912a6000 	add	x0, x0, #0xa98
  40082c:	52800001 	mov	w1, #0x0                   	// #0
  400830:	97ffff30 	bl	4004f0 <printf@plt>
  400834:	90000000 	adrp	x0, 400000 <_init-0x480>
  400838:	912a6000 	add	x0, x0, #0xa98
  40083c:	12800001 	mov	w1, #0xffffffff            	// #-1
  400840:	97ffff2c 	bl	4004f0 <printf@plt>
  400844:	90000000 	adrp	x0, 400000 <_init-0x480>
  400848:	912aa000 	add	x0, x0, #0xaa8
  40084c:	52800041 	mov	w1, #0x2                   	// #2
  400850:	97ffff28 	bl	4004f0 <printf@plt>
  400854:	90000000 	adrp	x0, 400000 <_init-0x480>
  400858:	912aa000 	add	x0, x0, #0xaa8
  40085c:	52800001 	mov	w1, #0x0                   	// #0
  400860:	97ffff24 	bl	4004f0 <printf@plt>
  400864:	d503201f 	nop
  400868:	a8c37bfd 	ldp	x29, x30, [sp], #48
  40086c:	d65f03c0 	ret

0000000000400870 <main>:
  400870:	a9a67bfd 	stp	x29, x30, [sp, #-416]!
  400874:	910003fd 	mov	x29, sp
  400878:	97ffff98 	bl	4006d8 <array_cal>
  40087c:	97ffffbc 	bl	40076c <enum_color_sizeof>
  400880:	97ffffc4 	bl	400790 <a_and_a>
  400884:	97ffffd5 	bl	4007d8 <planar_array>
  400888:	52800000 	mov	w0, #0x0                   	// #0
  40088c:	a8da7bfd 	ldp	x29, x30, [sp], #416
  400890:	d65f03c0 	ret
  400894:	00000000 	.inst	0x00000000 ; undefined

0000000000400898 <__libc_csu_init>:
  400898:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  40089c:	910003fd 	mov	x29, sp
  4008a0:	a901d7f4 	stp	x20, x21, [sp, #24]
  4008a4:	90000094 	adrp	x20, 410000 <__FRAME_END__+0xf538>
  4008a8:	90000095 	adrp	x21, 410000 <__FRAME_END__+0xf538>
  4008ac:	91374294 	add	x20, x20, #0xdd0
  4008b0:	913722b5 	add	x21, x21, #0xdc8
  4008b4:	a902dff6 	stp	x22, x23, [sp, #40]
  4008b8:	cb150294 	sub	x20, x20, x21
  4008bc:	f9001ff8 	str	x24, [sp, #56]
  4008c0:	2a0003f6 	mov	w22, w0
  4008c4:	aa0103f7 	mov	x23, x1
  4008c8:	9343fe94 	asr	x20, x20, #3
  4008cc:	aa0203f8 	mov	x24, x2
  4008d0:	97fffeec 	bl	400480 <_init>
  4008d4:	b4000194 	cbz	x20, 400904 <__libc_csu_init+0x6c>
  4008d8:	f9000bb3 	str	x19, [x29, #16]
  4008dc:	d2800013 	mov	x19, #0x0                   	// #0
  4008e0:	f8737aa3 	ldr	x3, [x21, x19, lsl #3]
  4008e4:	aa1803e2 	mov	x2, x24
  4008e8:	aa1703e1 	mov	x1, x23
  4008ec:	2a1603e0 	mov	w0, w22
  4008f0:	91000673 	add	x19, x19, #0x1
  4008f4:	d63f0060 	blr	x3
  4008f8:	eb13029f 	cmp	x20, x19
  4008fc:	54ffff21 	b.ne	4008e0 <__libc_csu_init+0x48>  // b.any
  400900:	f9400bb3 	ldr	x19, [x29, #16]
  400904:	a941d7f4 	ldp	x20, x21, [sp, #24]
  400908:	a942dff6 	ldp	x22, x23, [sp, #40]
  40090c:	f9401ff8 	ldr	x24, [sp, #56]
  400910:	a8c47bfd 	ldp	x29, x30, [sp], #64
  400914:	d65f03c0 	ret

0000000000400918 <__libc_csu_fini>:
  400918:	d65f03c0 	ret

Disassembly of section .fini:

000000000040091c <_fini>:
  40091c:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  400920:	910003fd 	mov	x29, sp
  400924:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400928:	d65f03c0 	ret
